Cadence launches Maestro suite of domain-specific AI models for chip design

On October 26, 2026, Cadence Design Systems launched Cadence Maestro, a portfolio of domain-specific AI models integrated with Nvidia Nemotron technology and OpenShell safety controls. Built for chip and system design, Maestro allows semiconductor companies to run fine-tuned models on-premises or in cloud environments. Cadence claims initial results show up to 30% higher design quality and 5X token efficiency over general-purpose models. The move contrasts with rival Synopsys, which partnered with OpenAI for hosted infrastructure.

Technical architecture and tool integration

• ▪Cadence Maestro models operate with Cadence's AI Super Agents, including AuraStack, ChipStack, InnoStack, and ViraStack, to orchestrate engineering tasks, models, and tools
• ▪Cadence Maestro connects AI agents to electronic design automation tools, evaluation harnesses, and deterministic solvers to create closed reinforcement-learning feedback loops based on measured outcomes
• ▪Cadence Maestro relies on deterministic electronic design automation tools for execution, analysis, and verification, using AI models primarily for planning, reasoning, and interpretation
• ▪Cadence Maestro models are specialized, post-trained AI models grounded in electronic design automation tools, domain knowledge, curated engineering data, and deterministic solvers

Customer customization and deployment flexibility

• ▪Cadence Design Systems allows customers to post-train and fine-tune Cadence Maestro models using their own proprietary chip design experiences and data
• ▪Cadence Design Systems enables customers to deploy Cadence Maestro models on Cadence's cloud, public clouds, or on-premises behind in-house firewalls

Collaboration with Nvidia on security

• ▪Cadence Design Systems built Cadence Maestro in part using Nvidia's open-weight Nemotron models and secured the platform with Nvidia's OpenShell safety technology
• ▪Cadence Design Systems and Nvidia are collaborating to secure AI agents that access proprietary chip designs, internal documentation, source code, and implementation flows

Early customer adoption

• ▪Silicon Labs implemented Cadence's ChipStack and Verisium Debug for faster root-cause analysis in low-power pre-silicon verification
• ▪Socionext is deploying Cadence's InnoStack Super Agent in physical design workflows to achieve productivity gains

Executive commentary on models

• ▪Cadence Senior Vice President Paul Cunningham stated that there are more AI model providers than chip design software vendors
• ▪Cadence Senior Vice President Paul Cunningham stated that Cadence is pursuing open- and closed-weight model approaches equally as part of the Cadence Maestro vision