Nvidia unveils NVHBM memory architecture, moving controller into HBM stack to free 25% more compute

Aug 31, 2026

Nvidia has unveiled its custom NVHBM memory architecture, which moves the memory controller directly into the HBM base die. This design frees up to 25% more compute area on custom AI accelerators while boosting bandwidth by 30% and cutting power draw by 15%. To drive adoption, Nvidia announced an expanded partnership with MediaTek, backed by a $3.5 billion convertible bond investment, positioning MediaTek as the primary integration gateway for third-party custom chips using Nvidia's NVLink Fusion platform.

NVHBM memory architecture

▪Nvidia's NVHBM architecture increases memory bandwidth per stack by up to 30% and reduces HBM power consumption by up to 15% compared to standard HBM4e.
▪Nvidia's NVHBM architecture shrinks the physical interface (PHY) and supporting area on the XPU compute die by up to 67% compared to the JEDEC HBM4e standard.
▪Nvidia announced its NVHBM memory architecture, which moves the memory controller off the processor chip and integrates it directly into the high-bandwidth memory (HBM) base die.
▪Nvidia's NVHBM architecture frees up to 25% more of an accelerator's main compute die area for compute logic or other features.

MediaTek partnership investment

▪Nvidia and MediaTek committed to co-develop future generations of DGX Spark and RTX Spark chip lines, following the October 2025 launch of the co-designed GB10 Grace Blackwell Superchip.
▪Nvidia invested $3.5 billion in convertible bonds issued by MediaTek as part of an expanded partnership announced on August 31, 2026.
▪Under their August 31, 2026 agreement, MediaTek will serve as the integration and manufacturing partner for custom XPUs that adopt Nvidia's NVLink Fusion and NVHBM architectures.

NVLink Fusion licensing strategy

▪Nvidia's NVLink Fusion platform includes the NVLink Fusion chiplet, which bridges custom XPUs to Nvidia's NVLink fabric using a Universal Chiplet Interconnect Express (UCIe) bridge.
▪Nvidia's NVLink Fusion platform licenses its proprietary networking and semiconductor IP, allowing third-party chip designers to integrate Nvidia's high-speed interconnects into custom accelerators.
▪Nvidia's senior director of HPC and AI Hyperscale Infrastructure, Dion Harris, confirmed that Nvidia will charge licensing fees for its NVLink Fusion technology.

Custom AI accelerator ecosystem

▪Amazon's Annapurna Labs is the first announced partner collaborating with Nvidia to integrate both NVHBM and NVLink Fusion into its upcoming Trainium4 AI accelerators.
▪The UALink Consortium, which includes Nvidia rivals AMD, Intel, Meta, and Microsoft, published the competing UALink 2.0 open-standard interconnect specification in April 2026.

Data center performance gains

▪Nvidia's sixth-generation NVLink scale-up fabric delivers 260 terabytes per second of aggregate bandwidth in a single 72-chip domain.
▪As of September 2026, no independent benchmark organization has published physical measurements of a shipping NVHBM-equipped accelerator.
▪Nvidia claims that the architectural improvements of NVHBM translate to a 30% end-to-end performance increase for custom XPUs.