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Aug 24, 2026

d-Matrix unveils Raptor AI accelerator with 100 TB/s bandwidth using stacked DRAM architecture

d-Matrix presented Raptor at Hot Chips 2026, featuring a TSMC 4nm compute die bonded face-to-face at 36-micron pitch directly onto custom DRAM, achieving 100 terabytes per second memory bandwidth while using one-sixth the energy per bit of HBM3.

Aug 24, 2026·2 sources
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Aug 4, 2026

SK hynix and SanDisk Release First High Bandwidth Flash (HBF) Standard Specification for AI Systems

SK hynix and SanDisk unveiled the first technical specification for High Bandwidth Flash (HBF), a new memory technology designed to bridge the performance gap between HBM and SSDs in AI accelerators, offering up to 3 TB/s bandwidth and terabyte-scale capacity. The specification was announced at the FMS 2026 conference, six months after the consortium's formation, with support from Google and Tenstorrent.

Aug 4, 2026·8 sources
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Top claims

  • ▪An ISCA 2026 paper co-written by d-Matrix and the University of British Columbia projects that the Raptor architecture delivers approximately 4.7 times higher throughput per card than HBM-based designs.
  • ▪The vertical microbump interface in the d-Matrix Raptor operates at an energy cost of 0.37 picojoules per bit, which is roughly six times lower than HBM3 across an interposer.
  • ▪At Hot Chips 2026, d-Matrix unveiled Raptor, a 3D DRAM accelerator for generative AI inference that delivers 100 TB/s of memory bandwidth from 32GB of capacity per card.

Subtopics

Compute, chips & AI infrastructure2AI hardware1AI inference (scaling)1Memory technology1

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