ASML, TSMC, Samsung and Intel form consortium to develop 12-inch photomasks for AI chips

Sep 8, 2026

ASML, TSMC, Samsung, and Intel have formed the Large Mask Consortium to transition the semiconductor industry from 6-inch to 12-inch photomasks. The shift addresses physical limitations in ASML's $400 million High-NA EUV systems, where anamorphic optics halve the exposure field. This constraint forces chipmakers to stitch exposures for large AI chips, causing a 30% throughput loss. The consortium targets a 12-inch pilot line by 2031 and production readiness by 2033 to restore full-field printing.

12-inch photomask consortium formation

▪SK Hynix is separately evaluating whether to join the Large Mask Consortium.
▪Intel Foundry and Samsung Electronics voiced their support and committed to the 12-inch photomask initiative, formally called the Large Mask Consortium.
▪ASML and TSMC launched a joint initiative on September 7 and 8, 2026, to transition the semiconductor industry from 6-inch photomasks to a new 12-inch format.

High-NA EUV optical constraints

▪The anamorphic optics in High-NA EUV systems shrink the wafer exposure field to 26 mm by 16.5 mm, which is half the area of conventional EUV shots.
▪ASML's High-NA EUV systems adopt an anamorphic optical design that demagnifies mask patterns by 4x horizontally and 8x vertically to prevent beam overlap at higher numerical apertures.

Stitching complexity from smaller exposure field

▪Reticle stitching forces chip designers to build seam boundaries into floor plans, adding design rules, alignment requirements, process complexity, and potential yield risks.
▪Reticle stitching on High-NA EUV scanners reduces wafer output from approximately 175 wafers per hour to around 125 wafers per hour, representing a 30% productivity loss.
▪Large chip dies exceeding the 26 mm by 16.5 mm High-NA EUV exposure field require reticle stitching, where two overlapping half-fields are exposed and aligned at a seam.

Throughput gains from larger masks

▪Transitioning to a 12-inch photomask format restores the full 26 mm by 33 mm exposure field, eliminating the 30% throughput penalty for large dies.
▪ASML Chief Technology Officer Marco Pieters stated that transitioning to 12-inch masks will increase the scanner productivity of High-NA EUV systems by 40%.

2031 pilot line target

▪The Large Mask Consortium aims to have supporting lithography systems ready for advanced-node semiconductor production by 2033.
▪Intel Foundry disclosed that it has led a parallel 6x12-inch large-format mask effort for more than three years prior to the September 2026 announcement.
▪The Large Mask Consortium targets establishing a 12-inch photomask pilot line by 2031.

AI chip size requirements

▪Processors designed by Nvidia and Google already reach sizes of about 800 square millimeters, which sits at the ceiling of what current 6-inch mask tools can print in a single exposure.
▪TSMC expects the number of layers requiring High-NA EUV will rise as new process nodes are introduced, driven by complex transistor architectures for AI applications.